VLSI DESIGN OF DIGITAL CORRELATORS FOR GPS RECEIVERS

M., Bahnas; M., Al-Imam; F., Regale H.

doi:10.21608/asat.2001.59742

VLSI DESIGN OF DIGITAL CORRELATORS FOR GPS RECEIVERS

Document Type : Original Article

Authors

¹ IC Design Consultant, Mentor Graphics Egypt, Cairo, Egypt.

² Graduate, Electronics & Communications Engineering Dept., Ain Shams Univ., Egypt.

³ Professor, Electronics & Communications Engineering Dept., Ain Shams Univ., Egypt.

10.21608/asat.2001.59742

Abstract

There are an increasing number of applications requiring precise relative position and clock-offset information. The Global Positioning System has demonstrated precise and drift free position and timing information using Code-Division-Multiple-Access (CDMA) spread spectrum technology. From the most interesting applications are the navigation and guidance, they are severely needed in the aviation field. .Detecting this accurately with no aid or dependence on anybody is an achieving step towards increasing the safety factors in the plane flights besides many other applications. This paper explores the GPS system as a whole, then targets to a certain objective. The main objective is to make a VLSI design and implementation for the main digital baseband block in the GPS receiver, the Digital Correlator. We designed 3 architectures, which are the serial, parallel and hybrid Correlators. Each of the serial and the parallel has pros & cons, which are discussed in details. There is a trade-off between the preferred small chip area and the quick response of the GPS receiver to its related stimulus. We finally reached to an optimized design gathering some advantages of both of them, the hybrid correlator. Using Mentor Graphics tools, the design is implemented in ASIC layout and FPGA chip.

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