This paper presents a real time implementation of Run-Length Encode (RLE) using FPGA as one of image compression algorithms. The RLE algorithm can be implemented either on commercial DSP or as an ASIC but due to the huge development in the FPGA field, it is recommended to use the FPGA technology. The design steps from design entry to files which are needed for the download process are developed.
Salama, G., Hassan, F., Sharrawy, M., & Bahy, R. (2011). AN IMPLEMENTATION OF THE RUN-LENGTH ENCODE ALGORITHM USING FPGA. International Conference on Aerospace Sciences and Aviation Technology, 11(ASAT Conference, 17-19 May 2005), 947-954. doi: 10.21608/asat.2011.27208
MLA
Gouda I. Salama; Fawzy ELtohamy Hassan; M. Sharrawy; Ramy M. Bahy. "AN IMPLEMENTATION OF THE RUN-LENGTH ENCODE ALGORITHM USING FPGA". International Conference on Aerospace Sciences and Aviation Technology, 11, ASAT Conference, 17-19 May 2005, 2011, 947-954. doi: 10.21608/asat.2011.27208
HARVARD
Salama, G., Hassan, F., Sharrawy, M., Bahy, R. (2011). 'AN IMPLEMENTATION OF THE RUN-LENGTH ENCODE ALGORITHM USING FPGA', International Conference on Aerospace Sciences and Aviation Technology, 11(ASAT Conference, 17-19 May 2005), pp. 947-954. doi: 10.21608/asat.2011.27208
VANCOUVER
Salama, G., Hassan, F., Sharrawy, M., Bahy, R. AN IMPLEMENTATION OF THE RUN-LENGTH ENCODE ALGORITHM USING FPGA. International Conference on Aerospace Sciences and Aviation Technology, 2011; 11(ASAT Conference, 17-19 May 2005): 947-954. doi: 10.21608/asat.2011.27208
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