DESIGN AND IMPLEMENTATION OF IDEA ALGORITHM KEY SCHEDULE ON FPGA

Shehata, Khaled; Hamdy, Nabil; Elagooz, Salah; Helmy, M.

doi:10.21608/asat.2013.24692

DESIGN AND IMPLEMENTATION OF IDEA ALGORITHM KEY SCHEDULE ON FPGA

Document Type : Original Article

Authors

¹ Assoc. Prof., AAST Communication Dept.

² MOD Signal Dept.

³ Assoc. Prof., MTC Communication Dept.

⁴ MTC Communication Dept.

10.21608/asat.2013.24692

Abstract

In this paper the design and implementation of the International Data Encryption Algorithm (IDEA) key schedule is presented. The IDEA key schedule takes 128-bit input key and returns 52 subkeys each of 16 bits during the encryption or the decryption operation. The key schedule includes the design of the inverse modulo (216+ 1) multiplier and the
inverse modulo 216 adder. The inverse modulo multiplier circuit is used to generate 18 inverse multiplicative keys and the inverse modulo adder circuit is used to generate 18 inverse additive keys. The inverse multiplicative key is calculated through multiplying the key to the power (216- 1) modulo (216+ 1). A 16 bit counter controls the inverse modulo multiplier circuit during the modulo multiplication process. A zero state problem is denoted during the generation of the inverse multiplicative keys because 216 is treated as zero during the modulo (216+ 1) multiplication in the encryption process. The IDEA key schdule is implemented on Xilinx FPGA Spartan II family and the target chip is XC2S100-5PQ208C.

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