Design of Low Voltage 1st Order 3-Bit Quantizer SR ΔΣ Modulator Using SR Op-Amp

Document Type : Original Article

Authors

1 Dr., Electronics & comm. Eng. Dept., Faculty of Eng., Mansoura university.

2 Prof., Electronics & comm. Eng. Dept., Faculty of Eng., Mansoura university.

3 Researcher assistant, Electronics & comm. Eng. Dept., Faculty of Eng., Mansoura university.

Abstract

This paper presents a low power (LP) switched resistor (SR) ΔΣ modulator based on 3-bit dynamic quantizer. The proposed design offers lower noise compared to switched capacitor (SC) techniques due to reduction of the number of switches and capacitors. The modulator is designed in a 0.18 μm CMOS technology. The total power consumption is 17.4 mW , and signal to noise ratio (SNR)= 65.8 dB, using, over sampling ratio (OSR) = 64 and 3 V power supply.

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