FPGA Implementation of Reconfigurable Parameters AES Algorithm

Rohiem, A. E.; Ahmed, F. M.; Mustafa, A. M.

doi:10.21608/asat.2009.23495

FPGA Implementation of Reconfigurable Parameters AES Algorithm

Document Type : Original Article

Authors

Egyptian Armed Forces.

10.21608/asat.2009.23495

Abstract

In this paper, a novel method of using customized (AES) variable parameters is introduced. This method depends on a continuous parameters reconfiguration and a customization of each internal block. The customization depends on varying the four transformations (polynomial and affine transformations for S-Box (SB), ShiftRows (SR) transformation, and MixColumn (MC) transformation). Internal AES blocks (SB, SR, and MC) are varied each round. Further more, these blocks are randomly interconnected during each session. The ciphered output was tested using avalanche, strict avalanche, and other NIST tests. This method overcomes (ECB) mode problems which appear when there is high redundancy in the plain data and also increasing strength against brute force attacks. The proposed AES is implemented on Field programmable Gate Arrays (FPGAs).

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