TY - JOUR ID - 197820 TI - Design and Implementation of an Advanced Radar Signal Processor with Waveform Generator and BIST Unit on a Single FPGA Chip JO - International Conference on Aerospace Sciences and Aviation Technology JA - ASAT LA - en SN - 2090-0678 AU - Abdel Razek, Ahmed M. AU - Ahmed, Fathy M AU - Kamel, Hazem AU - Mahfouz, Wael AU - Moustafa, K. H. AD - Radar Department, Military Technical College, Cairo, Egypt. Y1 - 2019 PY - 2019 VL - 18 IS - 18 SP - 1 EP - 10 KW - Radar KW - Matched Filter KW - Barker Code KW - FPGA KW - VHDL KW - MTI KW - CFAR DO - 10.1088/1757-899X/610/1/012095 N2 - Field Programmable Gate Arrays (FPGAs) are best suited for signal processing applications that require real-time processing. Therefore, it is preferred over DSP processors in implementing radar receivers that processes incoming continuous stream of data. In the past, implementing complex arithmetic operations in floating point representation was a monopoly on DSP processors and the designers had to work around the sequential nature of the DSP processor to make it suitable for real-time applications by using buffered and multi-clocking designs. But nowadays, the great advances in FPGA design technology minimized this design effort since it is capable of performing these complex algorithms in real time. This paper represents the design and implementation of an advanced radar signal processor for binary phase-coded pulsed radar incorporating a time range side lobes suppression technique on a single FPGA chip. The proposed hardware design includes a waveform generator, an advanced signal processing unit, and a built-in self-test (BIST). Design aspects and hardware details for each part is introduced thoroughly. UR - https://asat.journals.ekb.eg/article_197820.html L1 - https://asat.journals.ekb.eg/article_197820_2c248ce11d2ea0ecfbd6ab69a54c68fd.pdf ER -